1. Field of the Invention
The present invention relates to the field of semiconductor packages and, more particularly, to a semiconductor chip package.
2. Description of the Related Art
Wire bonding is used to make electrical connections between central processing unit (CPU) chips and semiconductor packages. Flip-chip technologies have been employed to package high-speed semiconductor devices. There are two types of semiconductor package structures formed using the flip-chip technologies; a lid type and a non-lid type. The lid type structure is typically used in chip packages that include a high-frequency CPU chip that generates a large quantity of heat. The non-lid type structure is generally used in chip packages that have a low-frequency CPU chip that generates a relatively small quantity of heat.
FIGS. 1 and 2 show a conventional semiconductor chip package 100 having a lid 40. Electrode bumps 24 of a CPU chip 20 are attached to the upper surface 12 of a substrate 10 using flip-chip technology. The CPU chip 20 is covered with a lid 40. A plurality of external connection pins 30, are electrically connected to the CPU chip 20, extend from the lower surface 14 of the substrate 10. An epoxy resin 52 fills an area between the CPU chip 20 and the substrate 10 to provide an under-fill adhesive.
The lid 40 is made of a material having a good heat emissive capacity. In order to maximize the heat emissive capacity through the lid 40, a thermal interface material (TIM) 56 is interposed between a bottom surface 42 of the lid 40 and a back surface of the CPU chip 20. A non-conductive adhesive 54, (e.g., a non-conductive thermosetting silicone adhesive) is used as a sealant for attaching the lid 40 to the upper surface 12 of the substrate 10. After applying the non-conductive adhesive 54 to the periphery of the substrate 10, the lid 40 is attached and the non-conductive adhesive 54 is cured (hardened). Thus, the space on which the CPU chip 20 is mounted is encapsulated.
The TIM can be a thermal grease type material, or a rigid type material (such as epoxy or solder). The thermal grease type has a thermal conductivity of 1 to 6 W/mk. Epoxy has a thermal conductivity of 10 to 25 W/mk and solder has a thermal conductivity of 25 to 80 W/mk.
In a conventional semiconductor package 100, the TIM 56 is interposed between the lid 40 and the CPU chip 20. In this arrangement, damage may occur depending on the type of TIM 56 used. In a CPU chip, a single chip type cache SRAM is recently employed to improve interface speed in the system. In this case, a localized area of thermal stresses, such as a hot spot, may occur. The term “Hot spot,” as used herein, refers to a local area where excessive heat is generated. As device power increases, the hot spot increases in size and/or number. When power reaches a predetermined level, the hot spot effects are greater than the other thermal stress factors. Thus, such a hot spot can degrade the performance of the CPU chip 20. In order to prevent the CPU chip 20 from being degraded, heat generated from the hot spot should be dissipated uniformly over the CPU chip 20 and emitted away from the CPU. However, the conventional TIM 56 does not have enough heat dissipation capability sufficient to dissipate the heat to a level as required above.
The thermal grease type TIM absorbs the thermomechanical stresses between the lid 40 and the CPU chip 20, but has a poor heat emissive capacity. On the other hand, the rigid type TIM, such as solder, has a good heat emissive capacity, but is less capable of absorbing the thermomechanical stresses between the lid 40 and the CPU chip 20. As a result, cracks can occur in the TIM 56 itself or in the CPU chip 20. Thermomechanical stresses arise due to differences in the coefficients of thermal expansion (CTE) between the lid 40, the CPU chip 20 and TIM 56. These CTE differences are commonly referred to as a “CTE mismatch.”
Accordingly, a need arises for a semiconductor package that has a good heat emissive capacity and has an improved structure for absorbing thermomechanical stress.